| Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
| u0|rst_controller|alt_rst_req_sync_uq1 |
2 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|rst_controller|alt_rst_sync_uq1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|rst_controller |
33 |
31 |
0 |
31 |
2 |
31 |
31 |
31 |
0 |
0 |
0 |
0 |
0 |
| u0|irq_mapper |
4 |
30 |
2 |
30 |
32 |
30 |
30 |
30 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|rsp_mux_001|arb|adder |
8 |
4 |
0 |
4 |
4 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|rsp_mux_001|arb |
6 |
0 |
4 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|rsp_mux_001 |
209 |
0 |
0 |
0 |
105 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|rsp_mux|arb|adder |
32 |
16 |
0 |
16 |
16 |
16 |
16 |
16 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|rsp_mux|arb |
12 |
0 |
4 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|rsp_mux |
827 |
0 |
0 |
0 |
111 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|rsp_demux_007 |
106 |
1 |
2 |
1 |
104 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|rsp_demux_006 |
106 |
1 |
2 |
1 |
104 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|rsp_demux_005 |
106 |
1 |
2 |
1 |
104 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|rsp_demux_004 |
106 |
1 |
2 |
1 |
104 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|rsp_demux_003 |
106 |
1 |
2 |
1 |
104 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|rsp_demux_002 |
107 |
4 |
2 |
4 |
207 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|rsp_demux_001 |
107 |
4 |
2 |
4 |
207 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|rsp_demux |
106 |
1 |
2 |
1 |
104 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux_007 |
106 |
0 |
2 |
0 |
104 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux_006 |
106 |
0 |
2 |
0 |
104 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux_005 |
106 |
0 |
2 |
0 |
104 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux_004 |
106 |
0 |
2 |
0 |
104 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux_003 |
106 |
0 |
2 |
0 |
104 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux_002|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux_002|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux_002 |
209 |
0 |
0 |
0 |
105 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux_001|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux_001|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux_001 |
209 |
0 |
0 |
0 |
105 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux |
106 |
0 |
2 |
0 |
104 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_demux_001 |
107 |
4 |
2 |
4 |
207 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_demux |
113 |
64 |
2 |
64 |
825 |
64 |
64 |
64 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_009|the_default_decode |
0 |
8 |
0 |
8 |
8 |
8 |
8 |
8 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_009 |
98 |
0 |
2 |
0 |
104 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_008|the_default_decode |
0 |
8 |
0 |
8 |
8 |
8 |
8 |
8 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_008 |
98 |
0 |
2 |
0 |
104 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_007|the_default_decode |
0 |
8 |
0 |
8 |
8 |
8 |
8 |
8 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_007 |
98 |
0 |
2 |
0 |
104 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_006|the_default_decode |
0 |
8 |
0 |
8 |
8 |
8 |
8 |
8 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_006 |
98 |
0 |
2 |
0 |
104 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_005|the_default_decode |
0 |
8 |
0 |
8 |
8 |
8 |
8 |
8 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_005 |
98 |
0 |
2 |
0 |
104 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_004|the_default_decode |
0 |
8 |
0 |
8 |
8 |
8 |
8 |
8 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_004 |
98 |
0 |
2 |
0 |
104 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_003|the_default_decode |
0 |
8 |
0 |
8 |
8 |
8 |
8 |
8 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_003 |
98 |
0 |
2 |
0 |
104 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_002|the_default_decode |
0 |
8 |
0 |
8 |
8 |
8 |
8 |
8 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_002 |
98 |
0 |
2 |
0 |
104 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_001|the_default_decode |
0 |
11 |
0 |
11 |
11 |
11 |
11 |
11 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_001 |
98 |
0 |
5 |
0 |
104 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router|the_default_decode |
0 |
11 |
0 |
11 |
11 |
11 |
11 |
11 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router |
98 |
0 |
5 |
0 |
104 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|modular_adc_0_sequencer_csr_agent_rsp_fifo |
138 |
39 |
0 |
39 |
97 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|modular_adc_0_sequencer_csr_agent|uncompressor |
32 |
1 |
0 |
1 |
30 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|modular_adc_0_sequencer_csr_agent |
276 |
39 |
45 |
39 |
288 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|modular_adc_0_sample_store_csr_agent_rsp_fifo |
138 |
39 |
0 |
39 |
97 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|modular_adc_0_sample_store_csr_agent|uncompressor |
32 |
1 |
0 |
1 |
30 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|modular_adc_0_sample_store_csr_agent |
276 |
39 |
45 |
39 |
288 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|lcd_ctrl_pio_s1_agent_rsp_fifo |
138 |
39 |
0 |
39 |
97 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|lcd_ctrl_pio_s1_agent|uncompressor |
32 |
1 |
0 |
1 |
30 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|lcd_ctrl_pio_s1_agent |
276 |
39 |
45 |
39 |
288 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|lcd_data_pio_s1_agent_rsp_fifo |
138 |
39 |
0 |
39 |
97 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|lcd_data_pio_s1_agent|uncompressor |
32 |
1 |
0 |
1 |
30 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|lcd_data_pio_s1_agent |
276 |
39 |
45 |
39 |
288 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|led_pio_s1_agent_rsp_fifo |
138 |
39 |
0 |
39 |
97 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|led_pio_s1_agent|uncompressor |
32 |
1 |
0 |
1 |
30 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|led_pio_s1_agent |
276 |
39 |
45 |
39 |
288 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|onchip_memory_s1_agent_rsp_fifo |
138 |
39 |
0 |
39 |
97 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|onchip_memory_s1_agent|uncompressor |
32 |
1 |
0 |
1 |
30 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|onchip_memory_s1_agent |
276 |
39 |
45 |
39 |
288 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|nios2_gen2_debug_mem_slave_agent_rsp_fifo |
138 |
39 |
0 |
39 |
97 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|nios2_gen2_debug_mem_slave_agent|uncompressor |
32 |
1 |
0 |
1 |
30 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|nios2_gen2_debug_mem_slave_agent |
276 |
39 |
45 |
39 |
288 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|jtag_uart_avalon_jtag_slave_agent_rsp_fifo |
138 |
39 |
0 |
39 |
97 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|jtag_uart_avalon_jtag_slave_agent|uncompressor |
32 |
1 |
0 |
1 |
30 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|jtag_uart_avalon_jtag_slave_agent |
276 |
39 |
45 |
39 |
288 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|nios2_gen2_instruction_master_agent |
165 |
37 |
71 |
37 |
130 |
37 |
37 |
37 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|nios2_gen2_data_master_agent |
165 |
37 |
71 |
37 |
130 |
37 |
37 |
37 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|modular_adc_0_sequencer_csr_translator |
99 |
6 |
15 |
6 |
69 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|modular_adc_0_sample_store_csr_translator |
99 |
6 |
9 |
6 |
75 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|lcd_ctrl_pio_s1_translator |
99 |
6 |
16 |
6 |
71 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|lcd_data_pio_s1_translator |
99 |
6 |
16 |
6 |
71 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|led_pio_s1_translator |
99 |
6 |
17 |
6 |
70 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|onchip_memory_s1_translator |
99 |
7 |
3 |
7 |
86 |
7 |
7 |
7 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|nios2_gen2_debug_mem_slave_translator |
99 |
5 |
7 |
5 |
82 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|jtag_uart_avalon_jtag_slave_translator |
99 |
5 |
18 |
5 |
70 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|nios2_gen2_instruction_master_translator |
100 |
51 |
0 |
51 |
92 |
51 |
51 |
51 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|nios2_gen2_data_master_translator |
100 |
12 |
0 |
12 |
92 |
12 |
12 |
12 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0 |
332 |
0 |
0 |
0 |
388 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|onchip_memory|the_altsyncram|auto_generated |
52 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|onchip_memory |
55 |
0 |
1 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen2|cpu|the_m10_adc_lcd_nios2_gen2_cpu_nios2_oci|the_m10_adc_lcd_nios2_gen2_cpu_debug_slave_wrapper|the_m10_adc_lcd_nios2_gen2_cpu_debug_slave_sysclk |
43 |
0 |
0 |
0 |
51 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen2|cpu|the_m10_adc_lcd_nios2_gen2_cpu_nios2_oci|the_m10_adc_lcd_nios2_gen2_cpu_debug_slave_wrapper|the_m10_adc_lcd_nios2_gen2_cpu_debug_slave_tck |
130 |
0 |
1 |
0 |
43 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen2|cpu|the_m10_adc_lcd_nios2_gen2_cpu_nios2_oci|the_m10_adc_lcd_nios2_gen2_cpu_debug_slave_wrapper |
123 |
0 |
0 |
0 |
53 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen2|cpu|the_m10_adc_lcd_nios2_gen2_cpu_nios2_oci|the_m10_adc_lcd_nios2_gen2_cpu_nios2_ocimem|m10_adc_lcd_nios2_gen2_cpu_ociram_sp_ram|the_altsyncram|auto_generated |
47 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen2|cpu|the_m10_adc_lcd_nios2_gen2_cpu_nios2_oci|the_m10_adc_lcd_nios2_gen2_cpu_nios2_ocimem|m10_adc_lcd_nios2_gen2_cpu_ociram_sp_ram |
47 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen2|cpu|the_m10_adc_lcd_nios2_gen2_cpu_nios2_oci|the_m10_adc_lcd_nios2_gen2_cpu_nios2_ocimem |
92 |
0 |
6 |
0 |
65 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen2|cpu|the_m10_adc_lcd_nios2_gen2_cpu_nios2_oci|the_m10_adc_lcd_nios2_gen2_cpu_nios2_avalon_reg |
48 |
0 |
28 |
0 |
68 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen2|cpu|the_m10_adc_lcd_nios2_gen2_cpu_nios2_oci|the_m10_adc_lcd_nios2_gen2_cpu_nios2_oci_im |
96 |
36 |
92 |
36 |
48 |
36 |
36 |
36 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen2|cpu|the_m10_adc_lcd_nios2_gen2_cpu_nios2_oci|the_m10_adc_lcd_nios2_gen2_cpu_nios2_oci_pib |
0 |
36 |
0 |
36 |
36 |
36 |
36 |
36 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen2|cpu|the_m10_adc_lcd_nios2_gen2_cpu_nios2_oci|the_m10_adc_lcd_nios2_gen2_cpu_nios2_oci_fifo|the_m10_adc_lcd_nios2_gen2_cpu_oci_test_bench |
36 |
0 |
36 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen2|cpu|the_m10_adc_lcd_nios2_gen2_cpu_nios2_oci|the_m10_adc_lcd_nios2_gen2_cpu_nios2_oci_fifo|the_m10_adc_lcd_nios2_gen2_cpu_nios2_oci_fifo_cnt_inc |
5 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen2|cpu|the_m10_adc_lcd_nios2_gen2_cpu_nios2_oci|the_m10_adc_lcd_nios2_gen2_cpu_nios2_oci_fifo|the_m10_adc_lcd_nios2_gen2_cpu_nios2_oci_fifo_wrptr_inc |
4 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen2|cpu|the_m10_adc_lcd_nios2_gen2_cpu_nios2_oci|the_m10_adc_lcd_nios2_gen2_cpu_nios2_oci_fifo|the_m10_adc_lcd_nios2_gen2_cpu_nios2_oci_compute_input_tm_cnt |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen2|cpu|the_m10_adc_lcd_nios2_gen2_cpu_nios2_oci|the_m10_adc_lcd_nios2_gen2_cpu_nios2_oci_fifo |
151 |
0 |
65 |
0 |
36 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen2|cpu|the_m10_adc_lcd_nios2_gen2_cpu_nios2_oci|the_m10_adc_lcd_nios2_gen2_cpu_nios2_oci_dtrace|m10_adc_lcd_nios2_gen2_cpu_nios2_oci_trc_ctrl_td_mode |
9 |
0 |
6 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen2|cpu|the_m10_adc_lcd_nios2_gen2_cpu_nios2_oci|the_m10_adc_lcd_nios2_gen2_cpu_nios2_oci_dtrace |
101 |
0 |
90 |
0 |
72 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen2|cpu|the_m10_adc_lcd_nios2_gen2_cpu_nios2_oci|the_m10_adc_lcd_nios2_gen2_cpu_nios2_oci_itrace |
25 |
17 |
23 |
17 |
87 |
17 |
17 |
17 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen2|cpu|the_m10_adc_lcd_nios2_gen2_cpu_nios2_oci|the_m10_adc_lcd_nios2_gen2_cpu_nios2_oci_dbrk |
86 |
0 |
0 |
0 |
90 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen2|cpu|the_m10_adc_lcd_nios2_gen2_cpu_nios2_oci|the_m10_adc_lcd_nios2_gen2_cpu_nios2_oci_xbrk |
52 |
5 |
49 |
5 |
6 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen2|cpu|the_m10_adc_lcd_nios2_gen2_cpu_nios2_oci|the_m10_adc_lcd_nios2_gen2_cpu_nios2_oci_break |
51 |
36 |
6 |
36 |
71 |
36 |
36 |
36 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen2|cpu|the_m10_adc_lcd_nios2_gen2_cpu_nios2_oci|the_m10_adc_lcd_nios2_gen2_cpu_nios2_oci_debug |
50 |
1 |
30 |
1 |
7 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen2|cpu|the_m10_adc_lcd_nios2_gen2_cpu_nios2_oci |
154 |
0 |
0 |
0 |
69 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen2|cpu|m10_adc_lcd_nios2_gen2_cpu_register_bank_b|the_altsyncram|auto_generated |
44 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen2|cpu|m10_adc_lcd_nios2_gen2_cpu_register_bank_b |
44 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen2|cpu|m10_adc_lcd_nios2_gen2_cpu_register_bank_a|the_altsyncram|auto_generated |
44 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen2|cpu|m10_adc_lcd_nios2_gen2_cpu_register_bank_a |
44 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen2|cpu|the_m10_adc_lcd_nios2_gen2_cpu_test_bench |
282 |
3 |
248 |
3 |
33 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen2|cpu |
149 |
1 |
30 |
1 |
107 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2_gen2 |
149 |
0 |
0 |
0 |
105 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|modular_adc_0|sample_store_internal|u_ss_ram|altsyncram_component|auto_generated |
31 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|modular_adc_0|sample_store_internal|u_ss_ram |
31 |
4 |
0 |
4 |
16 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| u0|modular_adc_0|sample_store_internal |
63 |
0 |
37 |
0 |
33 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|modular_adc_0|sequencer_internal|u_seq_ctrl |
8 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|modular_adc_0|sequencer_internal|u_seq_csr |
38 |
0 |
28 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|modular_adc_0|sequencer_internal |
38 |
0 |
0 |
0 |
40 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|modular_adc_0|control_internal|adc_inst|adcblock_instance |
9 |
0 |
0 |
0 |
14 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|modular_adc_0|control_internal|adc_inst|decoder |
5 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|modular_adc_0|control_internal|adc_inst |
9 |
0 |
0 |
0 |
14 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|modular_adc_0|control_internal|u_control_fsm |
25 |
0 |
0 |
0 |
29 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|modular_adc_0|control_internal |
12 |
0 |
0 |
0 |
21 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|modular_adc_0 |
80 |
0 |
0 |
0 |
65 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|led_pio |
38 |
27 |
27 |
27 |
37 |
27 |
27 |
27 |
0 |
0 |
0 |
0 |
0 |
| u0|lcd_data_pio |
39 |
28 |
28 |
28 |
36 |
28 |
28 |
28 |
0 |
0 |
0 |
0 |
0 |
| u0|lcd_ctrl_pio |
39 |
30 |
30 |
30 |
34 |
30 |
30 |
30 |
0 |
0 |
0 |
0 |
0 |
| u0|jtag_uart|the_m10_adc_lcd_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|wr_ptr |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|jtag_uart|the_m10_adc_lcd_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|rd_ptr_count |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|jtag_uart|the_m10_adc_lcd_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|FIFOram|altsyncram1 |
24 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|jtag_uart|the_m10_adc_lcd_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|FIFOram |
24 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|jtag_uart|the_m10_adc_lcd_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state|count_usedw |
5 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|jtag_uart|the_m10_adc_lcd_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state |
5 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|jtag_uart|the_m10_adc_lcd_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo |
13 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|jtag_uart|the_m10_adc_lcd_jtag_uart_scfifo_r|rfifo|auto_generated |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|jtag_uart|the_m10_adc_lcd_jtag_uart_scfifo_r |
13 |
0 |
1 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|jtag_uart|the_m10_adc_lcd_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|wr_ptr |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|jtag_uart|the_m10_adc_lcd_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|rd_ptr_count |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|jtag_uart|the_m10_adc_lcd_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|FIFOram|altsyncram1 |
24 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|jtag_uart|the_m10_adc_lcd_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|FIFOram |
24 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|jtag_uart|the_m10_adc_lcd_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state|count_usedw |
5 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|jtag_uart|the_m10_adc_lcd_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state |
5 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|jtag_uart|the_m10_adc_lcd_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo |
13 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|jtag_uart|the_m10_adc_lcd_jtag_uart_scfifo_w|wfifo|auto_generated |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|jtag_uart|the_m10_adc_lcd_jtag_uart_scfifo_w |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|jtag_uart |
38 |
10 |
23 |
10 |
34 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
| u0 |
4 |
0 |
0 |
0 |
11 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| upll|altpll_component|auto_generated |
3 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| upll |
2 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |